1. Field of the Invention
The present invention generally relates to testing of integrated circuit devices including memory structures and systems including such integrated circuits and, more particularly, to extending built-in self-test (BIST) arrangements to systems testing.
2. Description of the Prior Art
Increases in integration density of integrated circuits has greatly increased the performance and functionality of the circuits which can be included on a single semiconductor chip. Increased functionality, of course, requires increased circuit complexity and, at the present state of the art, many functionally differentiated regions such as adders, processors, logic arrays, buffers, decoders level converters and the like may be included on a single chip. These functionally differentiated regions are often designed to operate at different clock rates and even different voltages while being required to communicate with each other in a generally synchronized fashion.
Design of storage devices and processes for their fabrication have become quite sophisticated and have resulted in very low process cost for fabrication and very small memory cell area. Therefore it is currently practical to form even relatively large numbers of storage cells together with digital signal processing circuitry on a single chip. Moreover, use of multi-port memories for communication between functional components on a chip has proven to be extremely fast and efficient and thus has come into relatively widespread use. These memories are generally referred to as embedded memories when included with circuits having other than a storage function on an integrated circuit chip.
Nevertheless, memory sells, particularly of the dynamic type which store data capacitively, are relatively delicate devices and may be subject to damage or deterioration during manufacture or after being placed in service. When such devices are used for communication and data transfer among functional regions or components, the reliability of storage devices becomes extremely critical to the proper operation of the entire chip. Therefore, it is desirable to test storage cells at different stages of manufacture, board assembly and during system operation. This test is done periodically or at certain system operating states such as power-up of the chip in order to ascertain operability of the memory structures. It is also desirable to provide for broader testing of the various functional elements of the system operating together. Such tests are generally referred to as system level tests by cannot generally be performed by programmable memory BIST arrangements as will be discussed below.
Nevertheless, system failures may be attributed to damage caused by external elements, minor manufacturing imperfections and/or aging of the materials, Damage from external elements could impact the correct functioning of an electronic system or any part thereof at any time during its useable life. However, minor manufacturing imperfections are the main cause of system failures at early stages of system operation while aging is the dominant cause of system failures at, later stages of the time of the system. For high reliability and availability applications such as banking and medical applications, it is essential to perform periodic testing of system modules.
Memory devices are usually in the critical path of a system or its respective components and therefore their design is directed to ensure that memories in critical paths operate several times faster than their surrounding logic which is realized through aggressive design utilizing dense fabrication and new technologies. These factors may make embedded memories somewhat more prone to failures due to minor manufacturing imperfections and aging and thus must be tested periodically after being placed in service in addition to manufacturing level and board level testing.
Further, system level tests could be performed by dedicated hardware, independent of that used for manufacturing level and board level tests. However, in such a case, the hardware dedicated to manufacturing level and board level testing which is generally provided as a built-in self-test arrangement would have no function after the system is placed in service while the additional hardware provided for system level testing would increase the hardware overhead for testing of all types.
However, access to embedded memories for testing is often difficult, particularly where chip space and external connections are at a premium. For that reason, it is preferred to form a self-test circuit on the chip, itself. Numerous types of such arrangements are known and generally referred to as a built-in self-test (BIST) circuit or engine. Some forms of BIST circuits have been developed which allow the test sequence to be dynamically modified based on results of test procedures in order to accelerate the testing process. The amount of chip space which can be efficiently allocated to a BIST arrangement is very limited, generally to about 2% of the area of the storage devices to be tested.
This area must also include space for an instruction or signal source, such as a read-only-memory (ROM) and, usually, a decoder, to generate the coded digital signals with which the embedded memory is to be exercised during the self-test operation. At the present state of the art, maintaining the BIST arrangement within such a chip area constraint presents a major challenge, particularly where the memory structure is complex and extended numbers of sequences of signals are required to adequately test the memory and/or to capture signals from the memory for evaluation in the course of the self-test.
Even when the chip area is limited to a small percentage of the area of the memory to be tested, the chip space is considered to be inefficiently used since the BIST arrangement is not used in the other intended functions of the chip. Nevertheless, the use of a BIST arrangement may be the only practical technique for accessing the signal lines necessary for testing of an embedded memory. Accordingly, BIST architectures, including programmable memory BIST architectures which can alter the test procedure in response to test results, have been developed. Programmable BIST architectures also can accommodate different memory test signal patterns that may be required for different memory structures without significant hardware modification and associated design costs.
A programmable memory BIST arrangement often includes a programmable memory BIST controller and other components to generate the signals necessary to fully exercise and test the particular memory structure of interest. The programmable memory BIST controller generally includes a microcode-based controller and an instruction decode module which will develop one or more multi-bit signals (e.g. multi-bit data, address and control signals) for each instruction.
The instructions supported by the programmable memory BIST controller describe or constitute a memory test algorithm appropriate to the particular embedded memory to be tested and are stored in an instruction store module, preferably (or conceptually) within the microcode based controller. The instruction store module may be of any of a variety of forms including but not limited to a read only memory (ROM) such as an EEPROM or a register file. In the former case (e.g. where storage is non-volatile) no loading of the test instructions is necessary and may not be possible. Also, ROM and small RAM modules complicate the overall testing of the system.
Therefore, the use of a register file for storage of test instructions is generally preferred. In this case, the instructions for a particular desired test are loaded during the test process by means of an external tester. (It should be appreciated that while an external tester may be required for conducting a test procedure, the BIST may provide access to particular connections in the memory structures which are impractical to access otherwise.)
In a manufacturing level test (e.g. during chip manufacture and packaging) the supported instructions representing the test algorithm are input from an external tester as described above. If the storage elements in the register file are scannable, the loading process is performed serially using any scan protocol which has been adopted and/or which may be convenient. In board level testing in accordance with the IEEE 1149.1 standard, the register file is defined as a test data register and is accessed by loading an appropriate IEEE 1149.1 instruction in the instruction register. The memory test instructions are loaded using an external tester while the test access port (TAP) controller is in the SHIFT-DR state.
However, the BIST modules that use register files as their instruction store module cannot be used for system level tests. This is due to the fact that register files need to be initialized to the instruction set representing the test algorithm. Therefore, the BIST arrangement is confined to use in lower level tests where an external control of such initialization and source of test algorithm is available and thus represents a substantial inefficiency in utilization of chip space, as alluded to above, even though the BIST arrangement is substantially essential to assure functionality of a chip and the board which includes it.